As data transmission rates continue to increase, parallel data transmission in backplane and other interconnect applications suffer from effects such as co-channel interference and EMI. To ameliorate the problems associated with high-speed parallel data transmission, parallel data may be serialized before transmission and then de-serialized upon reception using serial transmission protocols such as a low voltage differential signaling protocol (LVDS) or differential current mode logic (CML). For example, LVDS uses high-speed circuit techniques to provide multi-gigabit data transfers on copper interconnects and is a generic interface standard for high-speed data transmission. LVDS system features, such as synchronizing data, encoding the clock and low skew, all work together for higher performance. Skew is a big problem for sending parallel data and its clock across cables or PCB traces because the phase relation of the data and clock can be lost as a result of different travel times through the link. However, the ability to serialize parallel data into a high-speed signal with an embedded clock eliminates the skew problem. The problem disappears because the clock travels with the data over the same differential pair of wires. The receiver uses a clock and data recovery circuit to extract the embedded-phase-aligned clock from the data stream. The recovered clock is then used by a data recovery component to identify the bits in the transmitted codeword.
To permit the transition between parallel and serial data transmission, serializer/deserializer (SERDES) circuits are incorporated at both the transmitting and receiving ends of the serial data stream. The resulting interfacing between high-speed serial data and low-speed parallel data transmission has lead to the development of interconnect structures that provide connectivity between SERDES input/output (I/O) data traffic and low-speed I/O data traffic. A number of alternative architectures have been developed to address connectivity of SERDES I/O with low-speed I/O such as field programmable gate arrays (FPGAs) having embedded SERDES, application specific standard product (ASSP), and programmable interconnect switches. FPGA approaches, however, suffer from non-deterministic routing delays and expensive overhead. Although ASSP approaches offer deterministic routing delays, they suffer from their lack of programmability in that users don't have the flexibility of assigning parallel I/O pins as desired. In contrast, the programmable interconnect approach offers the programmability advantages of FPGA approaches and the deterministic routing delay advantages of ASSPs without suffering from their associated drawbacks.
Turning now to FIG. 1, a block-based (which may also be denoted as “block-oriented) programmable interconnect circuit 25 is illustrated. As suggested by the “block-oriented” denotation, the input/output architecture for programmable interconnect circuit 25 includes a plurality of blocks 32 of I/O circuits (not illustrated). Each I/O circuit associates with a pin (not illustrated) for circuit 25 and includes input/output registers for the storage of incoming and outgoing signals over the pin. A routing structure 14 routes input and output signals amongst the blocks 32. The number of I/O circuits within each block 32 is arbitrary but may be conveniently matched to well-known bus widths such as 8 or 16 bits. In this fashion, the block-oriented architecture shown in FIG. 1 may accommodate bus-switching applications.
Each block 32 includes I/O cells that may communicate both low-speed I/O and high-speed (SERDES) I/O. As used herein, “high-speed data” refers to serial data provided to or from a SERDES. In that sense, a SERDES may receive serial data transmitted at a relatively high rate and deserialize the data into data words that are then transmitted at a relatively low rate. For example, an 8-bit parallel may be serialized in a transmitting SERDES into a 10-bit serial word that may be decoded into the same 8-bit parallel data word in a receiving SERDES. The actual data content would be the same for both serial and parallel transmission in that the 10-bit serial word only had a data content of 8 bits, the extra bits being used to provide sufficient edge transitions to encode a clock. Parallel data words that are not serialized and coupled through a SERDES but are instead just coupled through the programmable interconnect architecture are denoted herein as “low-speed data” or “low-speed I/O.” It will be appreciated, however, that what is relatively low speed about low-speed data is the word rate as compared to the serial bit transmission rate of high-speed data. For example, if serial high-speed data is transmitted at a certain bit rate, the same serial data may be de-serialized into 8-bit parallel data words and these words transmitted at a rate 8 times slower while still achieving the same overall data transmission rate. In that regard, transmission of low-speed data may achieve the same or higher overall data transmission rate as transmission of high-speed data.
Because each block 32 includes I/O cells that may communicate both high speed and low-speed data, each block 32 will require its own SERDES. The die area demands from SERDES circuits can be substantial. Accordingly, there is a need in the art for SERDES-containing programmable interconnect circuits that efficiently use die area.